AD7298(RevPrA) Ver la hoja de datos (PDF) - Analog Devices

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AD7298
(Rev.:RevPrA)

8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor

Analog Devices 

AD7298

Preliminary Technical Data

Figure 7. Partial Power Down Mode of Operation

FULL POWER-DOWN MODE

In this mode, all internal circuitry on the AD7298 is powered-

down and no information is retained in the control register or any

other internal register. If the averaging feature for the

temperature sensor is enabled in the control register

(TSENSEAVG), the averaging is reset once the device enters

power-down mode. The AD7298 is placed into full power-down

mode by bringing the logic level on the PD pin low for greater

than 100ns. The PD pin is asynchronous to the clock, hence it

can be triggered at any time. The part can be powered up for

normal operation by bringing the PD pin logic level back to a

high logic state. The full power-down feature can be used to

reduce the average power consumed by the AD7298 when

operating at lower throughput rates. The user should ensure

that tPOWER_UP has elapsed prior to programming the control

register and initiating a valid conversion.

POWERING UP THE AD7298

The AD7298 contains a power on reset circuit, which sets the

control register to its default setting of all zero’s, hence the

internal reference is enabled and the device is configured for

normal mode of operation. It takes 100μs to power up the

AD7298 when using the internal reference. When an external

reference is used TBD μs are required to power up the AD7298

with a 1μF decoupling capacitor.

When supplies are first applied to the AD7298, the user must

wait the specified power up time, tPOWER UP, before programming

the control register to select the desired channels for

conversion.

RESET

The AD7298 includes a reset feature, which can be used to reset

the device and the content of all internal registers including the

control register to their default state. To activate the reset

operation, the PD pin should be brought low for a minimum of

TBD ns and a maximum of 100ns and is asynchronous to the

clock, hence it can be triggered at any time. If the PD pin is held

low for greater than 100ns the part will enter full power-down

mode. It is imperative that the PD pin be held at a stable logic

level at all times to ensure normal operation.

Rev. PrA | Page 12 of 18

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