VDD = VREF = 5V
TA = 25°C
VDD
1
2
VOUT
CH1 2.0V CH2 500mV
MAX(C2)*
420.0mV
M100μs 125MS/s 8.0ns/pt
A CH1 1.28V
Figure 22. Power-On Reset to 0 V
VDD = VREF = 5V
TA = 25°C
VDD
1
2
VOUT
CH1 2.0V CH2 1.0V
M100μs 125MS/s 8.0ns/pt
A CH1 1.28V
Figure 23. Power-On Reset to Midscale
SCLK
1
2
VOUT
CH1 2.0V CH2 1.0V
M1.0μs 5.0gS/s 200ps/pt
A CH2 2.16V
Figure 24. Exiting Power-Down to Midscale
AD5662
2.502500
2.502250
2.502000
2.501750
2.501500
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
0
VDD = VREF = 5V
TA = 25°C
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
GLITCH IMPULSE = 2.723nV.s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 25. Digital-to-Analog Glitch Impulse (Negative)
2.500400
2.500300
2.500200
2.500100
2.500000
2.499900
2.499800
2.499700
2.499600
2.499500
2.499400
2.499300
2.499200
2.499100
0
VDD = VREF = 5V
TA = 25°C
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x7FFF TO 0x8000)
GLITCH IMPULSE = 1.271nV.s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 26. Digital-to-Analog Glitch Impulse (Positive)
2.500250
2.500200
2.500150
2.500100
2.500050
2.500000
2.499950
2.499900
2.499850
2.499800
2.499750
2.499700
2.499650
2.499600
0
VDD = VREF = 5V
TA = 25°C
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV.s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 27. Digital Feedthrough
Rev. A | Page 11 of 24