AD5668BRUZ-1REEL7 Ver la hoja de datos (PDF) - Analog Devices
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AD5668BRUZ-1REEL7
Analog Devices
AD5668BRUZ-1REEL7 Datasheet PDF : 30 Pages
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AD5628/AD5648/AD5668
Data Sheet
INPUT SHIFT REGISTER
The input shift register is 32 bits wide. The first four bits are
don’t cares. The next four bits are the command bits, C3 to C0
(see Table 9), followed by the 4-bit DAC address, A3 to A0 (see
Table 10) and finally the 16-/14-/12-bit data-word. The data-
word comprises the 16-/14-/12-bit input code followed by four,
six, or eight don’t care bits for the AD5668, AD5648, and
AD5628, respectively (see Figure 57 through Figure 59). These
data bits are transferred to the DAC register on the 32nd falling
edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
32 falling edges of SCLK, and the DAC is updated on the 32nd
falling edge and rising edge of SYNC. However, if SYNC is brought
high before the 32nd falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 60).
DB31 (MSB)
DB0 (LSB)
X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DATA BITS
DB31 (MSB)
COMMAND BITS
ADDRESS BITS
Figure 57. AD5668 Input Register Contents
DB0 (LSB)
X X X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
DATA BITS
DB31 (MSB)
COMMAND BITS
ADDRESS BITS
Figure 58. AD5648 Input Register Contents
DB0 (LSB)
X X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
DATA BITS
SCLK
COMMAND BITS
ADDRESS BITS
Figure 59. AD5628 Input Register Contents
SYNC
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB31
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
Figure 60. SYNC Interrupt Facility
Rev. J | Page 24 of 30
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