AD5530_02 Ver la hoja de datos (PDF) - Analog Devices
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AD5530_02 Datasheet PDF : 16 Pages
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AD5530/AD5531
+15V
2
6
8
VOUT
REFIN
VOUT
AD586
5
R1
10k⍀
AD5530/
AD5531*
C1
1F
4
DUTGND
VOUT
(–10V TO +10V)
SIGNAL
GND
REFAGND GND
VSS
–15V
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 5. Bipolar ±10 V Operation
2 REFIN
0V
–2 REFIN
DAC INPUT CODE 000 001
(3)FFF
ADSP-2101/
ADSP-2103*
FO
TFS
DT
SCLK
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 to 8051 Interface
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive SYNC and LDAC respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.
80C51/80L51*
P3.4
P3.3
RXD
TXD
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
Figure 6. Output Voltage vs. DAC Input Codes (Hex)
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC.
The contents of the DAC register may be read using the readback
function. RBEN is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.
Figure 8. AD5530/AD5531 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.
AD5530/AD5531 to ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control regis-
ter should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alternatively,
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
MC68HC11*
PC6
PC7
MOSI
SCK
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5530/AD5531 to MC68HC11 Interface
REV. 0
–11–
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