AD5415(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD5415
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5415 Datasheet PDF : 28 Pages
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TIMING CHARACTERISTICS
Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t122
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments1
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
AD5415
1 Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 4.
SCLK
SYNC
DIN
LDAC1
LDAC2
t8
t4
DB15
t6
t5
t1
t2
t3
t7
DB0
t10
t9
t11
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. 0 | Page 5 of 28
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