AD5124(RevA) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
fabricante
AD5124
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD5124 Datasheet PDF : 36 Pages
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Data Sheet
AD5124/AD5144/AD5144A
Parameter1
t12
tSP3
Test Conditions/Comments
Standard mode
Fast mode
Fast mode
Min
Typ Max
300
20 + 0.1 CL
300
0
50
Unit Description
ns Fall time of SCL signal, tFCL
ns
ns Pulse width of suppressed spike
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter
Min Typ Max Unit Description
t1
1
μs
End command to LRDAC falling edge
t2
50
ns
Minimum LRDAC low time
t3
0.1
10
μs
RESET low time
tEEPROM_PROGRAM1
tEEPROM_READBACK
tPOWER_UP2
15
50
7
30
75
ms
Memory program time (not shown in Figure 8)
μs
Memory readback time (not shown in Figure 8)
μs
Start-up time (not shown in Figure 8)
tRESET
30
μs
Reset EEPROM restore time (not shown in Figure 8)
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8 DB7
DB0 (LSB)
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BITS
DATA BITS
ADDRESS BITS
Figure 4. Input Shift Register Contents
SCL
t6
SDA
t7
PS
t11
t2
t4
t12
t6
t1
t5
t3
t10
S
Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence)
t8
t9
P
Rev. A | Page 11 of 36
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