74LVC1G53(2007) Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC1G53 Datasheet PDF : 22 Pages
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NXP Semiconductors
6. Pinning information
6.1 Pinning
74LVC1G53
Z1
E2
GND 3
GND 4
8 VCC
7 Y0
6 Y1
5S
001aad388
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
74LVC1G53
2-channel analog multiplexer/demultiplexer
74LVC1G53
Z1
8 VCC
E2
7 Y0
GND 3
6 Y1
GND 4
5S
001aad389
Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
terminal 1
index area
74LVC1G53
Y0 1
7Z
Y1 2
6E
S3
5 GND
Fig 5. Pin configuration SOT902-1 (XQFN8)
001aag459
Transparent top view
6.2 Pin description
Table 3.
Symbol
Z
E
GND
GND
S
Pin description
Pin
SOT505-2, SOT765-1 and SOT833-1
1
2
3
4
5
SOT902-1
7
6
5
4
3
Description
common output or input
enable input (active LOW)
ground (0 V)
ground (0 V)
select input
74LVC1G53_3
Product data sheet
Rev. 03 — 29 August 2007
© NXP B.V. 2007. All rights reserved.
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