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74LVC139D

Dual 2-to-4 line decoder/demultiplexer

Philips Electronics 

Philips Semiconductors

Dual 2-to-4 line decoder/demultiplexer

Product specification

74LVC139

FEATURES

• Wide supply voltage range of 1.2 to 3.6 V

• In accordance with JEDEC standard no. 8-1A

• Inputs accept voltages up to 5.5 V

• CMOS lower power consumption

• Direct interface with TTL levels

• Demultiplexing capability

• Two independent 2-to-4 decoders

• Multifunction capability

• Active LOW mutually exclusive outputs

• Output drive capability 50 W transmission lines at 85°C

DESCRIPTION

The 74LVC139 is a low-voltage, low-power, high-performance

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

The 74LVC139 is a dual 2-to-4 line decoder/demultiplexer. This device

has two independent decoders, each accepting two binary weighted

inputs (nA0 and nA1) and providing four mutually exclusive active LOW

outputs (nY0 to nY3). Each decoder has an active LOW input (nE).

When nE is HIGH, every output is forced HIGH. The enable can be

used as the data input for a 1-to-4 demultiplexer application.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

nA to nYn,

nE to nYn,

CL = 50 pF;

VCC = 3.3 V

CI

Input capacitance

CPD

Power dissipation capacitance per

multiplexer

VCC = 3.3 V

Notes 1 and 2

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL × VCC2 × fo) = sum of the outputs.

2. The condition is V1 = GND to VCC

TYPICAL

3.3

3.2

5.0

36

ORDERING INFORMATION

PACKAGES

16-Pin Plastic SO

16-Pin Plastic SSOP Type II

16-Pin Plastic TSSOP Type I

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74LVC139 D

–40°C to +85°C

74LVC139 DB

–40°C to +85°C

74LVC139 PW

NORTH AMERICA

74LVC139 D

74LVC139 DB

74LVC139PW DH

UNIT

ns

pF

pF

PKG. DWG. #

SOT109-1

SOT338-1

SOT403-1

PIN CONFIGURATION

1E 1

1A0 2

1A1 3

1Y0 4

1Y1 5

1Y2 6

1Y3 7

GND 8

16 VCC

15 2E

14 2A0

13 2A1

9 2Y0

10 2Y1

11 2Y2

12 2Y3

SV00530

PIN DESCRIPTION

PIN NUMBER SYMBOL

NAME AND FUNCTION

1, 15

1E, 2E Enable inputs (active LOW)

2, 3

14, 13

4, 5, 6, 7

12, 11, 10, 9

8

1A0, 1A1

2A0, 2A1

1Y0 to 1Y3

2Y0 to 2Y3

GND

Address inputs

Outputs (active LOW)

Ground (0 V)

16

VCC

Positive supply voltage

1998 Apr 28

2

853-2059 19309

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