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74LV165D Datasheet PDF : 20 Pages
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74LV165
8-bit parallel-in/serial-out shift register
6. Functional description
Table 3. Function table[1]
Operating modes Inputs
PL
CE
CP
DS
D0 to D7
parallel load
L
X
X
X
L
L
X
X
X
H
serial shift
H
L
l
X
H
L
h
X
hold “do nothing”
H
H
X
X
X
Qn registers
Q0
Q1 to Q6
L
L to L
H
H to H
L
q0 to q5
H
q0 to q5
q0
q1 to q6
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Output
Q7
Q7
L
H
H
L
q6
q6
q6
q6
q7
q7
&3
&(
'6
3/
'
'
'
'
'
'
'
'
4
4
Fig 6. Timing diagram
LQKLELW
ORDG
VHULDOVKLIW
PQD
74LV165
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 9 March 2016
© Nexperia B.V. 2017. All rights reserved
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