Preliminary
GS881E18/36AT-250/225/200/166/150/133
Flow Through Read-Write Cycle Timing
Single Read
Single Write
Burst Read
CK
ADSP
tS tH
tKC
tKH tKL
ADSP is blocked by E inactive
tS tH ADSC initiated read
ADSC
tS tH
ADV
A0-An
tS tH
RD1
WR1
RD2
GW
tS tH
tS
tH
BW
BA - BD
tS tH
WR1
tS tH
E1
E1 masks ADSP
G
DQA–DQD
tOE tOHZ
tKQ
Hi-Z
Q1A
tS tH
D1A
Q2A
Q2B
Q2c Q2D Q2A
Burst wrap around to it’s initial state
Rev: 1.01 3/2002
19/34
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.