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68HC05BD2

SPECIFICATION REV 2.0 (General Release)

Freescale Semiconductor 

MC68HC05BD7 RevF. 2r.e0escale SemicondGuEcNtoERr,AILnRcE.LEASE SPECIFICATION

SECTION 3

CPU CORE

The MC68HC05BD7 has a 16K memory map. Therefore it uses only the lower 14 bits of

the address bus. In the following discussion the upper 2 bits of the address bus can be

ignored. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only

6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other

instructions and registers behave as described in this chapter.

3.1 Registers

The MCU contains five registers which are hard-wired within the CPU and are not part of

the memory map. These five registers are shown in Figure 3-1 and are described in the

following paragraphs.

RY 7 6 5 4 3 2 1 0

AACCUMULATOR

A

ININDEX REGISTER

X

15 14 13 12 11 10 9 8

0000000011

STACK POINTER

SP

IM PROGRAM COUNTER

PC

L CONDITION CODE REGISTER 1 1 1 H I N Z C CC

EHALF-CARRY BIT (FROM BIT 3)

INTERRUPT MASK

R NEGATIVE BIT

P ZERO BIT

CARRY BIT

Figure 3-1: MC68HC05 Programming Model

3.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses

the accumulator to hold operands and results of arithmetic calculations or non-arithmetic

operations. The accumulator is not affected by a reset of the device.

SECTION 3: CPU CORE

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