56857 Ver la hoja de datos (PDF) - Freescale Semiconductor

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56857

16-bit Digital Signal Controllers

Freescale Semiconductor 

Introduction

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56857 are organized into functional groups, as shown in Table 2-1 and

as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals

present.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (VDD, VDDIO, or VDDA)

(8, 12, 1)1

Ground (VSS, VSSIO,or VSSA)

(5, 12, 2)1

PLL and Clock

3

Chip Select Logic used as dedicated GPIO

4

Interrupt and Program Control

72

Host Interface (HI)*

163

Enhanced Synchronous Serial Interface (ESSI0) Port*

6

Enhanced Synchronous Serial Interface (ESSI1) Port*

6

Serial Communications Interface (SCI0) Ports*

2

Serial Communications Interface (SCI1) Ports*

2

Serial Peripheral Interface (SPI) Port*

4

Quad Timer Module Port*

4

JTAG/Enhanced On-Chip Emulation (EOnCE)

6

*Alternately, GPIO pins

1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA

2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed.

3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.

56857 Technical Data, Rev. 6

Freescale Semiconductor

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