Architecture Block Diagram
To/From IPBus Bridge
TA0 on Figure 1-7
TA2 - 3 on Figure 1-7
2
PWM
PWM0 - 3
FAULT0
PWMA4 - 5
FAULT1
4
2
12
FAULT2
1
RELOAD PSRC0 - 2
FAULT3
GPIOA6
GPIOA0 - 3
GPIOA4 - 5
TA1 on Figure 1-7
GPIOB5
CMPAO on Figure 1-5
CMPBO on Figure 1-5
IPBus
3
3
GPIOB2 - 4 on Figure 1-4
3
LIMIT on Figure 1-3
3
TA0o, TA2o, TA3o on Figure 1-3
Figure 1-6 56F8033/56F8023 I/O Pin-Out Muxing (Part 4/5)
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
15