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AD7896AN

2.7 V to 5.5 V, 12-Bit, 8 μ
s ADC in 8-Lead SOIC/PDIP

Analog Devices 

AD7896

Dynamic Performance (Mode 1 Only)

With a combined conversion and acquisition time of 9.5 µs, the

AD7896 is ideal for wide bandwidth signal processing applications.

These applications require information on the ADC’s effect on the

spectral content of the input signal. Signal-to-(noise + distortion),

total harmonic distortion, peak harmonic or spurious noise, and

intermodulation distortion are all specified. Figure 11 shows a

typical FFT plot of a 10 kHz, 0 V to 3.3 V input after being digi-

tized by the AD7896 operating at a 102.4 kHz sampling rate.

The signal-to-(noise + distortion) ratio is 71.5 dB and the total

harmonic distortion is –82.4 dB.

–0

fSAMPLE = 102.4kHz

fIN = 10kHz

–20

SNR = 71.54dB

THD = –82.43dB

–40

–60

–80

–100

–120

0

10240

20480

30720

FREQUENCY (Hz)

40960

51200

Figure 11. AD7896 FFT Plot

Effective Number of Bits

The formula for signal-to-(noise + distortion) ratio (see the

Terminology section) is related to the resolution or number of

bits in the converter. Rewriting the formula below gives a mea-

sure of performance expressed in effective number of bits (N)

N = (SNR 1.76)/6.02

where SNR is the signal-to-(noise + distortion) ratio.

The effective number of bits for a device can be calculated from

its measured signal-to-(noise + distortion) ratio. Figure 12

shows a typical plot of effective number of bits versus frequency

for the AD7896 from dc to fSAMPLING/2. The sampling frequency

is 102.4 kHz. The plot shows that the AD7896 converts an input

sine wave of 51.2 kHz to an effective numbers of bits of 11.25,

which equates to a signal-to-(noise + distortion) level of 69 dB.

12.00

11.75

11.50

11.25

11.00

0

25.6

51.2

INPUT FREQUENCY (kHz)

Figure 12. Effective Number of Bits vs. Frequency

Power Considerations

In the automatic power-down mode, the part can be operated

at a sample rate that is considerably less than 100 kHz. In this

case, the power consumption will be reduced and will depend

on the sample rate. Figure 13 shows a graph of the power con-

sumption versus sampling rates from 10 Hz to 1 kHz in the

automatic power-down mode. The conditions are 2.7 V supply,

25°C, serial clock frequency of 8.33 MHz, and the data was

read after conversion.

200

fSCLK = 8.33MHz

160

120

80

40

0

10

100

1000

SAMPLING RATE IN Hz

Figure 13. Power vs. Sample Rate in Auto Power-

Down Mode

–12–

Rev. D

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