AD7684BRMZ Ver la hoja de datos (PDF) - Analog Devices
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AD7684BRMZ Datasheet PDF : 16 Pages
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AD7684
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to DOUT High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
DOUT Fall Time
DOUT Rise Time
Symbol
tCYC
tCSD
tSUCS
tHDO
tDIS
tEN
tACQ
tF
tR
Min
20
5
400
Typ Max
100
0
16
14 100
16 50
11 25
11 25
Timing Diagrams
CS
tSUCS
tCYC
COMPLETE CYCLE
POWER DOWN
DCLOCK
1
45
tCSD
tEN
tHDO
DOUT
Hi-Z
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
(MSB)
(LSB)
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
tACQ
tDIS
Hi-Z
Unit
kHz
μs
ns
ns
ns
ns
ns
ns
ns
500μA IOL
TO DOUT
CL
100pF
1.4V
500μA IOH
Figure 3. Load Circuit for Digital Interface Timing
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 4. Voltage Reference Levels for Timing
DOUT
tR
90%
10%
tF
Figure 5. DOUT Rise and Fall Timing
Rev. A | Page 5 of 16
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