AD9776ABSVZ Ver la hoja de datos (PDF) - Analog Devices
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AD9776ABSVZ Datasheet PDF : 56 Pages
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AD9776A/AD9778A/AD9779A
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
Maximum Input Data Rate at Interpolation
1×
2×
4×
8×
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High
Output VOUT Logic Low
DATACLK Output Duty Cycle
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
Setup Time, SYNC_I to REFCLK
Hold Time, SYNC_I to REFCLK
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, RO
DAC CLOCK INPUT (REFCLK+, REFCLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
Conditions
Min Typ Max Unit
2.0
V
0.8 V
DVDD18, CVDD18 = 1.8 V ± 5%
DVDD18, CVDD18 = 1.9 V ± 5%
DVDD18, CVDD18 = 2.0 V ± 2%
300
250
200
112.5
125
137.5
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
At 250 MHz, into 5 pF load
SYNC_I+ = VIA, SYNC_I− = VIB
Additional limits on fSYNC_I apply; see description of
Register 0x05, Bits[3:1], in Table 14
SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Single-ended
2.4
V
0.4 V
40 50 60 %
825
−100
20
80
0.4
0.55
1575
+100
120
250
mV
mV
mV
Ω
MSPS
ns
ns
1375 mV
1025
mV
150 200 250 mV
1150
1250 mV
80 100 120 Ω
DVDD18, CVDD18 = 1.8 V ± 5%, PLL off
DVDD18, CVDD18 = 1.9 V ± 5%, PLL off
DVDD18, CVDD18 = 2.0 V ± 2%, PLL off
DVDD18, CVDD18 = 2.0 V ± 2%, PLL on
400 800 2000 mV
300 400 500 mV
900
MHz
1000
MHz
1100
MHz
250
MHz
1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
Rev. B | Page 6 of 56
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