AD7663 Ver la hoja de datos (PDF) - Analog Devices
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AD7663 Datasheet PDF : 24 Pages
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AD7663
Parameter
Conditions
Min
Typ
Max
TEMPERATURE RANGE8
Specified Performance
TMIN to TMAX
–40
+85
NOTES
1LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5Tested in Parallel Reading Mode.
6Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.
7With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
8Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Range
IND(4R)
INC(4R)
±4 REF2
VIN
±2 REF
VIN
±REF
VIN
0 V to 4 REF
VIN
0 V to 2 REF
VIN
0 V to REF
VIN
INGND
VIN
VIN
VIN
VIN
VIN
NOTES
1Typical analog input impedance.
2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3For this range the input is high impedance.
INB(2R)
INGND
INGND
VIN
INGND
VIN
VIN
INA(R)
REF
REF
REF
INGND
INGND
VIN
Unit
°C
Input
Impedance1
5.85 kW
3.41 kW
2.56 kW
3.41 kW
2.56 kW
Note 3
TIMING SPECIFICATIONS (–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol Min
Typ
Max
Refer to Figures 11 and 12
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
t1
5
t2
4
t3
t4
t5
2
t6
10
t7
t8
2.75
t9
10
30
1.25
1.25
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
1.25
DATA Valid to BUSY LOW Delay
t11
20
Bus Access Request to DATA Valid
t12
40
Bus Relinquish Time
t13
5
15
Refer to Figures 17 and 18 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
t14
10
CS LOW to Internal SCLK Valid Delay
t15
10
CS LOW to SDOUT Delay
t16
10
CNVST LOW to SYNC Delay (Read during Convert)
t17
0.5
SYNC Asserted to SCLK First Edge Delay2
t18
4
Internal SCLK Period2
t19
25
40
Internal SCLK HIGH2
t20
15
Internal SCLK LOW2
t21
9.5
SDOUT Valid Setup Time2
t22
4.5
SDOUT Valid Hold Time2
t23
2
SCLK Last Edge to SYNC Delay2
t24
3
REV. B
–3–
Unit
ns
µs
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
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