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MAX19705ETM

10-Bit, 7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

10-Bit, 7.5Msps, Ultra-Low-Power

Analog Front-End

Pin Description (continued)

PIN

10

13–18, 21–24

19

20

25

26

27

28

29

30

34

35

36

37

38

40, 41

44, 45

46

47

48

—

NAME

FUNCTION

QAP Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.

D0–D9

Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most

significant bit (MSB) and D0 is the least significant bit (LSB).

OGND Output-Driver Ground

OVDD

Output-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a

combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.

SHDN Active-Low Shutdown Input. Apply logic-low to place the MAX19705 in shutdown.

DOUT

T/R

Aux-ADC Digital Output

Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A

logic-high input sets the device in transmit mode.

DIN

3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.

SCLK

CS

3-Wire Serial-Interface Clock Input

3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface.

ADC2 Analog Input for Auxiliary ADC

ADC1 Analog Input for Auxiliary ADC

DAC3 Analog Output for Auxiliary DAC3

DAC2

DAC1

IDN, IDP

Analog Output for Auxiliary DAC2

Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up)

DAC Channel-ID Differential Voltage Output

QDN, QDP DAC Channel-QD Differential Voltage Output

REFIN

COM

Reference Input. Connect to VDD for internal reference.

Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.

REFN

Negative Reference I/O. Rx ADC conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a

0.1µF capacitor.

EP

Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.

Detailed Description

The MAX19705 integrates a dual 10-bit Rx ADC and a

dual 10-bit Tx DAC while providing ultra-low power and

high dynamic performance at 7.5Msps conversion rate.

The Rx ADC analog input amplifiers are fully differential

and accept 1.024VP-P full-scale signals. The Tx DAC

analog outputs are fully differential with ±400mV full-

scale output, selectable common-mode DC level, and

adjustable I/Q offset trim.

The MAX19705 integrates three 12-bit auxiliary DAC

(aux-DAC) channels and a 10-bit, 333ksps auxiliary

ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC

channels feature 1µs settling time for fast AGC, VGA,

and AFC level setting. The aux-ADC features data aver-

aging to reduce processor overhead and a selectable

clock-divider to program the conversion rate.

The MAX19705 includes a 3-wire serial interface to

control operating modes and power management. The

serial interface is SPI™ and MICROWIRE™ compatible.

The MAX19705 serial interface selects shutdown, idle,

standby, transmit (Tx), and receive (Rx) modes, as well

as controlling aux-DAC and aux-ADC channels.

The Rx ADC and Tx DAC share a common digital I/O to

reduce the digital interface to a single 10-bit parallel

multiplexed bus. The 10-bit digital bus operates on a

single +1.8V to +3.3V supply.

SPI is a trademark of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

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