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53C810

PCI-SCSI I/O Processor

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PRELIMINARY

Chapter Five

Operating Registers

arbitration sequence is complete. If a se-

quence is aborted, bit 4 in the SCNTLI

register should be checked to verify that the

53C810 did not connect to the SCSI bus.

Bit 4 WATN (Select with ATN! on a start

. sequence)

When this bit is set and the 53C810 is in

initiator mode, the SCSI ATN/ signal will be

asserted during 53C81 0 selection of a target

device. This is to inform the target that the

53C810 has a message to send. Ifa selection

time-out occurs while attempting to select a

target device, ATN! will be deasserted at the

same time SEU is deasserted. When this bit is

clear, the ATN/ signal will not be asserted

during selection. When executing SCSI

SCRIPTS, this bit is controlled by the

SCRIPTS processor, but it may be set manu-

ally in low level mode.

Bit 3 EPC (Enable parity checking)

When this bit is set, the SCSI data bus is

checked for odd parity when data is received

from the SCSI bus in either initiator or target

mode. If a parity-error is detected, bit 0 of the

SISTO register is set and an interrupt may be

generated.

If the 53C810 is operating in initiator mode -

and a parity error is detected, ATN/ can

optionally be asserted, but the transfer contin-

ues until the target changes phase.

When this bit is cleared, parity errors are not

reported.

transfer with the parity error. The Enable

Parity Checking bit must also be set for the

53C810 to assert ATN/ in this manner. The

following parity errors can occur:

1) A parity error detected on data received

from the SCSI bus.

2) A parity error detected on data transferred

to the 53C810 from the host data bus.

If the Assert ATN/ on Parity Error bit is

cleared or the Enable Parity Checking bit is

cleared, ATN/ will not be automatically

asserted on the SCSI bus when a parity error

is received.

Bit 0 TRG (Target mode)

This bit determines the default operating

mode of the 53C810. The user must manually

set target or initiator mode. This can be done

using the SCRIPTS language (SET target or

CLEAR target). When this bit is set, the chip

is a target device by'default. When the target

mode bit is cleared, the 53C810 is an initiator

device by default.

CAUTION: writing this register while not con-

nected may cause the loss of a selection or rese-

lection due to the changing of target or initiator

modes.

Bit 2 Reserved

Bit 1 AAP (Assert ATN! on parity error)

When this bit is set, the 53C810 automatically

asserts the SCSI ATN/ signal upon detection

of a parity error. ATN! is only asserted in

initiator mode. The ATN/ signal is asserted

before deasserting ACKI during the byte

NCR 53C810 Data Manual

5-5

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