53C810 Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
fabricante
53C810 Datasheet PDF : 140 Pages
| |||
PRELIMINARY
Chapter Five
Operating Registers
Chapter Five
Operating Registers
This section contains descriptions of all 53C810 operating registers. Table 5-:-1 summarizes the 53C810
operating register set. Figure 5-1, the register map, lists registers by operating and configuration ad-
dresses. The terms "set" and "assert" are used to refer to bits that are programmed to a binary one.
Similarly, the terms "deasserr," "clear" and "reset" are used to refer to bits that are programmed to a
binary zero. Any bits marked as reserved should always be written to zero; mask all information read
from them. Reserved bit functions may be changed at any time. Unless otherwise indicated, all bits in
registers are active high, that is, the feature is enabled by setting the bit. The bottom of every register
diagram shows the default register values, which are enabled after the chip is powered on or reset.
The only register that the host CPU can access while the 53C810 is executing SCRIPTS is the ISTAT
register; attempts to access other registers will interfere with the operation of the chip. However, all
operating registers are accessible via SCRIPTS. All read data is synchronized and stable when presented
to the PCI bus.
Table 5-1. Operating Register Addresses and Descriptions
Memory
or 1/0
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10-13
14
18
19
lA
IB
lC-IF
Config
Mem/1/0
80
81
82
83
84
85
86
87
88 .
89
8A
8B
8C
8D
8E
8F
90-93
94
98
99
9A
9B
9C-9F
Readl
Write
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
R
RIW
R
R
R
R
RIW
RIW
RIW
R
R
R
RIW
Label
SCNTLO
SCNTLI
SCNTL2
SCNTL3
scm
SXFER
SDm
GPREG
SFBR
SOCL
SSID
SBCL
DSTAT
SSTATO
SSTATI
SSTAT2
DSA
ISTAT
CTESTO
CTESTI
CTEST2
CTEST3
TEMP
Description
SCSI Control 0
SCSI Control 1
SCSI Control 2
SCSI Control 3
SCSI ChipID
SCSI Transfer
SCSI Destination ID
General Purpose Bits
SCSI First Byte Received
SCSI Output Control Latch
SCSI Selector ID
SCSI Bus Control Lines
DMAStatus
SCSI Status 0
SCSI Status 1
SCSI Status 2
Data Structure Address
Interrupt Status
Chip Test 0
Chip Test 1
Chip Test 2
Chip Test 3
Temporary Stack
NCR 53C81 0 Data Manual
5-1
Share Link: 