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MCP41100-IP

Single/Dual Digital Potentiometer with SPI™ Interface

Microchip Technology 

MCP41XXX/42XXX

Absolute Maximum Ratings †

VDD...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V

Storage temperature .....................................-60°C to +150°C

Ambient temp. with power applied ................-60°C to +125°C

ESD protection on all pins ..................................................≥ 2 kV

† Notice: Stresses above those listed under “maximum rat-

ings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied. Expo-

sure to maximum rating conditions for extended periods may

affect device reliability.

AC TIMING CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.

Parameter

Sym

Min.

Typ.

Max.

Units

Conditions

Clock Frequency

FCLK

—

—

10

MHz VDD = 5V (Note 1)

Clock High Time

tHI

40

—

—

ns

Clock Low Time

tLO

40

—

—

ns

CS Fall to First Rising CLK Edge

tCSSR

40

—

—

ns

Data Input Setup Time

tSU

40

—

—

ns

Data Input Hold Time

tHD

10

—

—

ns

SCK Fall to SO Valid Propagation Delay

tDO

—

80

ns

CL = 30 pF (Note 2)

SCK Rise to CS Rise Hold Time

tCHS

30

—

—

ns

SCK Rise to CS Fall Delay

tCS0

10

—

—

ns

CS Rise to CLK Rise Hold

tCS1

100

—

—

ns

CS High Time

tCSH

40

—

—

ns

Reset Pulse Width

tRS

150

—

—

ns Note 2

RS Rising to CS Falling Delay Time

tRSCS

150

—

—

ns Note 2

CS rising to RS or SHDN falling delay time

tSE

40

—

—

ns Note 3

CS low time

tCSL

100

—

—

ns Note 3

Shutdown Pulse Width

tSH

150

—

—

ns Note 3

Note 1:

2:

When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay

time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI =

40 ns, tDO = 80 ns and tSU = 40 ns.

Applies only to the MCP42XXX devices.

3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.

 2003 Microchip Technology Inc.

DS11195C-page 5

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