MAX5734CCTN Ver la hoja de datos (PDF) - Maxim Integrated
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MAX5734CCTN Datasheet PDF : 26 Pages
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32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
TIMING CHARACTERISTICS—DVDD = +4.75V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
CLR Pulse-Width Low
SYMBOL
CONDITIONS
fSCLK
tCH
tCL
tSCS
tCSS
tCS1
At end of cycle in SPI mode only
tCS2
tDS
tDH
tSCL Load capacitance = 20pF
tSDH Load capacitance = 20pF
tCSPWH
tCSPWL
tLDAC
tCLR
MIN TYP MAX UNITS
0
33
MHz
10
ns
10
ns
6
ns
5
ns
15
ns
0
ns
10
ns
2
ns
20
ns
20
ns
50
ns
20
ns
20
ns
20
ns
TIMING CHARACTERISTICS—DVDD = +2.7V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
CLR Pulse-Width Low
SYMBOL
CONDITIONS
fSCLK
tCH
tCL
tSCS
tCSS
tCS1 At end of cycle in SPI mode only
tCS2
tDS
tDH
tSCL Load capacitance = 20pF
tSDH Load capacitance = 20pF
tCSPWH
tCSPWL
tLDAC
tCLR
MIN TYP MAX UNITS
0
25
MHz
10
ns
10
ns
10
ns
10
ns
18
ns
0
ns
10
ns
2
ns
25
ns
25
ns
50
ns
20
ns
20
ns
20
ns
10 ______________________________________________________________________________________
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