EP2C50AU208I7ES Ver la hoja de datos (PDF) - Altera Corporation

Número de pieza

componentes Descripción

fabricante

EP2C50AU208I7ES

Section I. Cyclone II Device Family Data Sheet

Altera Corporation 

Cyclone II Architecture

Embedded multipliers can operate at up to 250 MHz (for the fastest speed

grade) for 18 × 18 and 9 × 9 multiplications when using both input and

output registers.

Each Cyclone II device has one to three columns of embedded multipliers

that efficiently implement multiplication functions. An embedded

multiplier spans the height of one LAB row. Table 2–10 shows the number

of embedded multipliers in each Cyclone II device and the multipliers

that can be implemented.

Table 2–10. Number of Embedded Multipliers in Cyclone II Devices Note (1)

Device

EP2C5

EP2C8

EP2C15

EP2C20

EP2C35

EP2C50

EP2C70

Embedded

Multiplier Columns

1

1

1

1

1

2

3

Embedded

Multipliers

13

18

26

26

35

86

150

9 × 9 Multipliers 18 × 18 Multipliers

26

13

36

18

52

26

52

26

70

35

172

86

300

150

Note to Table 2–10:

(1) Each device has either the number of 9 × 9-, or 18 × 18-bit multipliers shown. The total number of multipliers for

each device is not the sum of all the multipliers.

The embedded multiplier consists of the following elements:

■ Multiplier block

■ Input and output registers

■ Input and output interfaces

Figure 2–18 shows the multiplier block architecture.

Altera Corporation

February 2007

2–33

Cyclone II Device Handbook, Volume 1

Share Link: