AD5424 Ver la hoja de datos (PDF) - Analog Devices
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AD5424 Datasheet PDF : 32 Pages
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AD5424/AD5433/AD5445
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
VDD = 2.5 V to 5.5 V
0
0
10
6
0
5
9
20
40
5
10
VDD = 4.5 V to 5.5 V
0
0
10
6
0
5
7
10
20
5
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns typ
ns max
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time (write cycle)
Data setup time
Data hold time
R/W high to CS low
CS min high time
Data access time
Bus relinquish time
1 Guaranteed by design, not subject to production test.
R/W
t1
t2
t6
t2
CS
DATA
t7
t3
t4
t5
t8
DATA VALID
Figure 2. Timing Diagram
t9
DATA VALID
Rev. B | Page 5 of 32
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