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AK8133

Low Spurious Multiclock Generator with XO

Asahi Kasei Microdevices 

AK8133

Typical Connection Diagram

+3.3V typ.

SW0

SW1

SW2

27.0MHz Crystal

Cext1

Cext2

AK8133

1:XOUT

XIN:16

2:S0

VDD3:15

3:S1

S3:14

4:S2

VDD2:13

5:VDD1

GND2:12

C1

6:GND1

CLK4:11

7:CLK1

CLK3:10

8:CLK2

REFOUT:9

C3

SW3

C2

SW0

SW1

SW2

Clock Output

A: Crystal connection

+3.3V typ.

AK8133

1:XOUT

XIN:16

2:S0

VDD3:15

3:S1

S3:14

4:S2

VDD2:13

5:VDD1

GND2:12

C1

6:GND1

CLK4:11

7:CLK1

CLK3:10

8:CLK2

REFOUT:9

GND

27MHz

External Clock

C3

SW3

C2

GND

Clock Output

B: External clock input

Figure 1: Typical Connection Diagram

C1-3 : 0.1µF

Cext1-2 : Depends on crystal characteristics. Refer the specification of the crystal.

Sw0-3 : Open is “H” and tied to GND is “L” for S0,S1ａｎｄ S3, because these pins have

internal pull up resister. For S2 tied VDD is “H” and tied GND is “L” .

MS0930-E-03

-6-

May-11

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