ST16C1451CQ48 Ver la hoja de datos (PDF) - Exar Corporation

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ST16C1451CQ48

2.97V TO 5.5V UART

Exar Corporation 

ST16C1450/51

2.97V TO 5.5V UART

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REV. 4.2.0

4.4.1 Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

• RXRDY is by received data in RHR.

• TXRDY is by THR empty.

• MSR is by any of the MSR bits 0, 1, 2 and 3.

4.4.2 Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that

generated the interrupt(s) has been emptied or cleared from RHR).

• RXRDY interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register AND disabling the TXRDY interrupt (set IER bit-1 =

0), or by loading data into the TX FIFO.

• MSR interrupt is cleared by a read to the MSR register.

]

TABLE 4: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY LEVEL

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

BIT-3 BIT-2 BIT-1

BIT-0

1

0

1

1

0 LSR (Receiver Line Status Register)

2

0

1

0

0 RXRDY (Received Data Ready)

3

0

0

1

0 TXRDY (Transmit Ready)

4

0

0

0

0 MSR (Modem Status Register)

-

0

0

0

1 None (default)

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 4).

ISR[7:4]: Reserved

4.5 Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

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