QLX411GRX Ver la hoja de datos (PDF) - Intersil
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QLX411GRX Datasheet PDF : 11 Pages
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QLx411GRx
Typical Application Reference Design
Figure 8 shows reference design schematics for a QLx411GRx evaluation board with an SMA connector interface.
1.2V
Detection threshold
reference voltage
EQ Boost Control
for Channels 1 and 2
Loss of signal indicator (Channels 1 and 2)
DT
1
IN1[P]
2
IN1[N]
3
1.2V
4
IN2[P]
5
IN2[N]
6
1.2V
7
IN3[P]
8
IN3[N]
9
1.2V
10
IN4[P]
11
IN4[N]
12
LOS1
13
LOS2
14
15
QLx411GRx
38
OUT1[P]
37
OUT1[N]
36
1.2V
35
OUT2[P]
34
OUT2[N]
33
1.2V
32
OUT3[P]
31
OUT3[N]
30
1.2V
29
OUT4[P]
28
OUT4[N]
27
LOS3
26
LOS4
25
24 GND
A
Loss of signal indicator (Channels 3 and 4)
1.2V
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
EQ Boost Control
for Channels 3 and 4
= SMA Connector
A) DC Blocking Capacitors = X7R or COG
0.1µF (>6GHz bandwidth)
QLx411GRx
LANE EXTENDER
Reference
Control Pin Mode
Quellan, Inc.
FIGURE 8. APPLICATION CIRCUIT FOR THE QLx411GRx EVALUATION BOARD SHOWING THE USE OF THE CONTROL
PINS FOR SETTING THE EQUALIZER COMPENSATION LEVEL
9
FN6989.1
November 19, 2009
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