QLX411GRX Ver la hoja de datos (PDF) - Intersil

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QLX411GRX

Quad Lane Extender

Intersil 

QLx411GRx

Pin Descriptions

PIN NAME PIN NUMBER

DESCRIPTION

DT

1

Detection Threshold. Reference DC voltage threshold for input signal power detection. Data

output OUT[k] is muted when the power of the equalized version of IN[k] falls below the

threshold. Tie to ground to disable electrical idle preservation and always enable the limiting

amplifier.

IN1[P,N]

2, 3

Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

VDD

4, 7, 10, 29, 32, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to

35

ground is recommended for each of these pins for broad high-frequency noise suppression.

IN2[P,N]

5, 6

Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

IN3[P,N]

8, 9

Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

IN4[P,N]

11, 12

Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

LOS1

13

LOS indicator 1. High output when equalized IN1 signal is below DT threshold.

LOS2

14

LOS indicator 2. High output when equalized IN2 signal is below DT threshold.

NC

15, 16, 18, 21, Not connected: Do not make any connections to these pins.

38, 41, 44, 45,

46

CP3[A,B,]

19, 20

Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

CP4[A,B,]

22, 23

Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

GND

24

This pin should be grounded.

LOS4

25

LOS indicator 4. High output when equalized IN1 signal is below DT threshold.

LOS3

26

LOS indicator 3. High output when equalized IN2 signal is below DT threshold.

OUT4[N,P]

27, 28

Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

OUT3[N,P]

30, 31

Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

OUT2[N,P]

33, 34

Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

OUT1[N,P]

36, 37

Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

6GHz frequency response is recommended.

CP2[B,A]

39, 40

Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

CP1[B,A]

42, 43

Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

EXPOSED

PAD

-

Exposed ground pad. For proper electrical and thermal performance, this pad should be

connected to the PCB ground plane.

3

FN6989.1

November 19, 2009

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