MT48LC16M16A2BG-6A Ver la hoja de datos (PDF) - Micron Technology

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MT48LC16M16A2BG-6A

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

SELF REFRESH Operation

SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the

system is powered down. When in self refresh mode, the device retains data without ex-

ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-

mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,

all the inputs to the device become “Don’t Care” with the exception of CKE, which must

remain LOW.

After self refresh mode is engaged, the device provides its own internal clocking, ena-

bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-

fresh mode for a minimum period equal to tRAS and remains in self refresh mode for an

indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK

must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling

within timing constraints specified for the clock ball.) After CKE is HIGH, the device

must have NOP commands issued for a minimum of two clocks for tXSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-

ing to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and

AUTO REFRESH utilize the row refresh counter.

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

81

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 1999 Micron Technology, Inc. All rights reserved.

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