256Mb: x4, x8, x16 SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature
Voltage on VDD/VDDQ supply relative to VSS
Voltage on inputs, NC, or I/O balls relative to VSS
Storage temperature (plastic)
Power dissipation
Symbol
VDD/VDDQ
VIN
TSTG
–
Min
–1
–1
–55
–
Max
4.6
4.6
150
1
Unit Notes
V
1
°C
W
Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.
Table 8: DC Electrical Characteristics and Operating Conditions
Notes 1–3 apply to all parameters and conditions; VDD/VDDQ = 3.3V ±0.3V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Supply voltage
VDD, VDDQ
3
3.6
V
Input high voltage: Logic 1; All inputs
VIH
2
VDD + 0.3
V
4
Input low voltage: Logic 0; All inputs
VIL
–0.3
0.8
V
4
Output high voltage: IOUT = –4mA
VOH
2.4
–
V
Output low voltage: IOUT = 4mA
VOL
–
0.4
V
Input leakage current: Any input 0V ≤ VIN ≤ VDD (All
IL
–5
5
μA
other balls not under test = 0V)
Output leakage current: DQ are disabled; 0V ≤ VOUT ≤
IOZ
–5
–5
μA
VDDQ
Operating temperature:
Commercial
TA
0
70
˚C
Industrial
TA
–40
85
˚C
Automotive
TA
–40
105
˚C
Notes:
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate cycle time at which proper opera-
tion over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤
TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)).
3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse
width ≤3ns.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
23
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© 1999 Micron Technology, Inc. All rights reserved.