MT47H128M8HW-25ELITH Ver la hoja de datos (PDF) - Micron Technology

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MT47H128M8HW-25ELITH

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be

changed with an EMRS set command. tMOD (MAX) updates the RTT setting.

Figure 82: Timing for MRS Command to ODT Update Delay

T0

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Command

EMRS1

NOP

NOP

NOP

NOP

NOP

CK#

CK

ODT2

Internal

RTT setting

tAOFD

0ns

Old setting

tMOD

Undefined

2

tIS

New setting

Indicates a break in

time scale

Notes:

1. The LM command is directed to the mode register, which updates the information in

EMR (A6, A2), that is, RTT (nominal).

2. To prevent any impedance glitch on the channel, the following conditions must be met:

tAOFD must be met before issuing the LM command; ODT must remain LOW for the en-

tire duration of the tMOD window until tMOD is met.

Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode

CK#

T0

T1

T2

T3

T4

T5

T6

CK

tCK

tCH tCL

Command

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Address

Valid

Valid

Valid

Valid

Valid

Valid

Valid

CKE

ODT

RTT

tAOND

tAOFD

tAON (MIN)

tAON (MAX)

RTT Unknown

tAOF (MAX)

tAOF (MIN)

RTT On

Don’t Care

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

129

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

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