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MT47H128M8HW-25ELITH

1Gb: x4, x8, x16 DDR2 SDRAM

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ODT Timing

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been ena-

bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-

gories. ODT will operate either in synchronous mode or asynchronous mode, depend-

ing on the state of CKE. ODT can switch anytime except during self refresh mode and a

few clocks after being enabled via EMR, as shown in Figure 81 (page 128).

There are two timing categories for ODT—turn-on and turn-off. During active mode

(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,

MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in

Figure 83 (page 129).

During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)

and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),

tAONPD and tAOFPD timing parameters are applied, as shown in Figure 84 (page 130).

ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-

rameter tANPD (MIN), as shown in Figure 85 (page 130). At state T2, the ODT HIGH sig-

nal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD

(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 85 (page 130) also

shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not oc-

cur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.

ODT turn-on timing prior to entering any power-down mode is determined by the pa-

rameter tANPD, as shown in Figure 86 (page 131). At state T2, the ODT HIGH signal sat-

isfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is

satisfied, tAOND and tAON timing parameters apply. Figure 86 (page 131) also shows

the example where tANPD (MIN) is not satisfied because ODT HIGH does not occur un-

til state T3. When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.

ODT turn-off timing after exiting any power-down mode is determined by the parame-

ter tAXPD (MIN), as shown in Figure 87 (page 132). At state Ta1, the ODT LOW signal

satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is

satisfied, tAOFD and tAOF timing parameters apply. Figure 87 (page 132) also shows the

example where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.

When tAXPD (MIN) is not satisfied, tAOFPD timing parameters apply.

ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-

er-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 88

(page 133). At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting pow-

er-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing pa-

rameters apply. Figure 88 (page 133) also shows the example where tAXPD (MIN) is not

satisfied because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied,

tAONPD timing parameters apply.

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

127

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