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MT46V4M32FK-4

DOUBLE DATA RATE (DDR) SDRAM

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READs (continued)

Data from any READ burst may be truncated with a

BURST TERMINATE command, as shown in Figure 11.

The BURST TERMINATE latency is equal to the READ

(CAS) latency, i.e., the BURST TERMINATE command

should be issued x cycles after the READ command,

where x equals the number of desired data element

pairs (pairs are required by the 2n-prefetch architec-

ture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can

be issued. If truncation is necessary, the BURST TER-

MINATE command must be used, as shown in Figure

12. The tDQSS (MIN) case is shown; the tDQSS (MAX)

case has a longer bus idle time. (tDQSS [MIN] and

tDQSS [MAX] are defined in the section on WRITEs.)

ADVANCE

128Mb: x32

DDR SDRAM

A READ burst may be followed by, or truncated with,

a PRECHARGE command to the same bank provided

that auto precharge was not activated. The

PRECHARGE command should be issued x cycles after

the READ command, where x equals the number of

desired data element pairs (pairs are required by the

2n-prefetch architecture). This is shown in Figure 13.

Following the PRECHARGE command, a subsequent

command to the same bank cannot be issued until tRP

is met. Note that part of the row precharge time is hid-

den during the access of the last data elements.

128Mb: x32 DDR SDRAM

4M32DDR_B.p65 – Rev. B, Pub. 7/02

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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