MK2771-12 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2771-12 Datasheet PDF : 4 Pages
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I CR O C LOC K
MK2771-12
VCXO and Set-Top Clock Source
Pin Assignment
PCS0 1
X2 2
X1 3
AVDD 4
VIN 5
VDD 6
GND 7
PCLK 8
UCLK 9
ACLK 10
20 ACS
19 UCS
18 27M
17 GND
16 27M
15 VDD
14 GND
13 11.06M
12 PCS1
11 13.5M
Processor Clock Select Table
PCS1 PCS0 PCLK (MHz)
0
0
50.000
0
1
16.667
M
0
test
M
1
32.000
1
0
40.000
1
1
20.000
0 = connect directly to ground, 1 = connect directly
to VDD, M = leave floating or unconnected
UART Clock Table
UCS UCLK (MHz)
0
18.432
1
3.6864
ACLK Select Table
ACS
ACLK (MHz)
0
49.152
1
24.576
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
PCS0
X2
X1
AVDD
VIN
VDD
GND
PCLK
UCLK
ACLK
13.5M
PCS1
11.06M
GND
VDD
27M
GND
27M
UCS
ACS
Type
I
O
I
P
I
P
P
O
O
O
O
TI
O
P
P
O
P
O
I
I
Description
Processor Clock Select 0. Selects PCLK on pin 8. See table above.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Analog VDD. Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to +5V.
Connect to ground.
Processor clock output determined by status of PCS1,0. See table above.
UART clock output determined by status of UCS. See table above.
49.152 MHz or 24.576 MHz clock output determined by ACS. See table above
13.5 MHz clock output. Divide by two of the 27MHz VCXO output.
Processor Clock Select 1. Selects PCLK on pin 8. See table above.
11.0592 MHz clock output.
Connect to ground.
Connect to +5V.
27.00 MHz VCXO clock output.
Connect to ground.
27.00 MHz VCXO clock output.
UART Clock Select. Selects UCLK on pin 9. See table above.
ACLK Select. Selects ACLK on pin 10. See table above.
Key: I = Input, TI = Tri-level input, O = output, P = power supply connection
MDS 2771-12 A
2
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
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