WRITE CYCLE 2 (S Controlled, See Notes 1 and 2)
MCM101524–12 MCM101524–15
Parameter
Symbol
Min
Max
Min
Max Unit
Write Cycle Time
tAVAV
12
—
15
—
ns
Address Setup Time
tAVSL
1
—
1
—
ns
Address Valid to End of Write
tAVSH
9
—
10
—
ns
Write Pulse Width
(S) tSLSH
8
—
9
—
ns
(W) tSLWH
Data Valid to End of Write
tDVSH
8
—
9
—
ns
Chip Select Set–Up Time
tSLWL
0
—
0
—
ns
Data Hold Time
tSHDX
1
—
1
—
ns
Write Recovery Time
tSHAX
1
—
1
—
ns
NOTES:
1. A write occurs during the overlap of S low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
Notes
3
A (ADDRESS)
S (CHIP SELECT)
tAVSL
D (DATA IN)
W (WRITE ENABLE)
tSLWL
WRITE CYCLE 2 (S Controlled, See Notes 1 and 2)
tAVAV
tAVSH
tSLSH
tSLWH
tDVSH
DATA VALID
tSHAX
tSHDX
Q (DATA OUT)
Motorola Memory Prefix
Part Number
ORDERING INFORMATION
(Order by Full Part Number)
MCM 101524 XX XX XX
Shipping Method (Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)
Package (TB = TAB)
Full Part Numbers — MCM101524TB12
MCM101524TB15
MCM101524
6
MOTOROLA FAST SRAM