Serial Peripheral Interface (SPI) Timing
SS
(Input)
SCLK (CPOL = 0)
(Input)
tC
tCL
tCH
tF
tR
tELG
SCLK (CPOL = 1)
(Input)
tELD
tCL
tA
tCH
tR
MISO
(Output)
tDS
MOSI
(Input)
Slave MSB out
Bits 14–1
MSB in
tDV
tDH
Bits 14–1
tF
tD
Slave LSB out
tDI
tDI
LSB in
Figure 10-11 SPI Slave Timing (CPHA = 0)
SS
(Input)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
tC
tCL
tELD
tR
tCH
tCL
tDV
tA
tDS
tCH
Slave MSB out
tF
Bits 14–1
MSB in
tDV
tDH
Bits 14–1
tF
tELG
tR
tD
Slave LSB out
tDI
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 1)
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
121
Preliminary