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MAX3691

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer

with Clock Synthesis and LVDS Inputs

_______________Detailed Description

The MAX3691 serializer comprises a 4-bit parallel input

register, a 4-bit shift register, control and timing logic, a

PECL output buffer, LVDS input/output buffers, and a

frequency-synthesizing PLL (consisting of a phase/

frequency detector, loop filter/amplifier, and voltage-

controlled oscillator). This device converts 4-bit-wide,

155Mbps data to 622Mbps serial data (Figure 1).

The PLL synthesizes an internal 622Mbps reference

used to clock the output shift register. This clock is

generated by locking onto the external 155.52MHz

reference-clock signal (RCLK).

The incoming parallel data is clocked into the

MAX3691 on the rising transition of the parallel-clock-

input signal (PCLKI). The control and timing logic

ensure proper operation if the parallel-input register is

latched within a window of time that is defined with

respect to the parallel-clock-output signal (PCLKO).

PCLKO is the synthesized 622Mbps internal serial-

clock signal divided by four. The allowable PCLKO-to-

PCLKI skew is -0.7ns to +3.3ns. This defines a timing

window at about the PCLKO rising edge, during which

a PCLKI rising edge may occur. Figure 2 is the timing

diagram.

PD3+

PD3-

PD2+

PD2-

PD1+

PD1-

PD0+

PD0-

PCLKI+

PCLKI-

RCLK+

RCLK-

LVDS

LVDS

LVDS

4-BIT

PARALLEL

INPUT

REGISTER

LVDS

LVDS

LVDS

PHASE/FREQ

DETECT

MAX3691

SHIFT

4-BIT

SHIFT

SD+

PECL

REGISTER

SD-

VCO

CONTROL

LATCH

LVDS

Figure 1. Functional Diagram

FIL+ FIL-

PCLKO+ PCLKO-

_______________________________________________________________________________________ 5

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