MAX11626(2014) Ver la hoja de datos (PDF) - Maxim Integrated
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MAX11626 Datasheet PDF : 22 Pages
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MAX11626–MAX11629/
MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Electrical Characteristics (continued)
(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE
= 300kHz, fSCLK = 4.8MHz external clock (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V
(MAX11626/MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)(Note 6)
Input Voltage Low
MAX11626/MAX11628/MAX11632
VIL
MAX11627/MAX11629/MAX11633
Input Voltage High
MAX11626/MAX11628/MAX11632
VIH
MAX11627/MAX11629/MAX11633
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (DOUT, EOC)
VHYST
IIN
CIN
VIN = 0V or VDD
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
VOL
VOH
IL
COUT
ISINK = 2mA
ISINK = 4mA
ISOURCE = 1.5mA
CS = VDD
CS = VDD
Supply Voltage
MAX11626/MAX11628/MAX11632
VDD
MAX11627/MAX11629/MAX11633
MAX11627/MAX11629/MAX11633
Supply Current (Note 7)
Internal
reference
IDD
External
reference
fSAMPLE = 300ksps
fSAMPLE = 0, REF on
Shutdown
fSAMPLE = 300ksps
Shutdown
MAX11626/MAX11628/MAX11632
Supply Current (Note 7)
Internal
reference
IDD
External
reference
fSAMPLE = 300ksps
fSAMPLE = 0, REF on
Shutdown
fSAMPLE = 300ksps
Shutdown
Power-Supply Rejection
PSR
VDD = 2.7V to 3.6V; full-scale input
VDD = 4.75V to 5.25V; full-scale input
MIN TYP MAX UNITS
0.8
V
VDD x 0.3
2.0
V
VDD x 0.7
200
mV
±0.01 ±1.0
µA
15
pF
0.4
V
0.8
VDD - 0.5
V
±0.05 ±1
µA
15
pF
4.75
5.25
V
2.7
3.6
1750 2000
1000 1200
0.2
5
µA
1050 1200
0.2
5
2300 2550
1050 1350
0.2
5
µA
1550 1700
0.2
5
±0.2
±1
mV
±0.2 ±1.4
Note 1: MAX11627/MAX11629/MAX11633 tested at VDD = +3V. MAX11626/MAX11628/MAX11632 tested at VDD = +5V.
Note 2: Offset nulled.
Note 3: Time for reference to power up and settle to within 1 LSB.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
Note 6: When CNVST is configured as a digital input, do not apply a voltage between VIL and VIH.
Note 7: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
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