CY7C1318BV18-200BZXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1318BV18-200BZXI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

TAP Controller State Diagram[9]

1

TEST-LOGIC

RESET

0

0

TEST-LOGIC/ 1

IDLE

SELECT

1

DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

1

1

EXIT1-DR

0

PAUSE-DR

0

1

0

EXIT2-DR

1

UPDATE-DR

1

0

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

1

SELECT

IR-SCAN

0

1

CAPTURE-IR

0

SHIFT-IR

0

1

EXIT1-IR

1

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

1

0

Document Number: 38-05621 Rev. *C

Page 14 of 28

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