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CS61318 Ver la hoja de datos (PDF) - Cirrus Logic

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componentes Descripción
fabricante
CS61318
CIRRUS
Cirrus Logic 
CS61318 Datasheet PDF : 28 Pages
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CS61318
Reading the control/status registers returns their
current status or setting. Control Register 1 (0x10))
outputs the status of NLOOP and LOS. Additional-
ly, 5, 6, and 7 encoded as shown in Tables 3.
2.12 Interrupts
An interrupt will occur (INT pulls low) in response
to a change in the LOS, AIS or NLOOP bits. The
interrupt is cleared when the host processor writes
a “1” to the respective bit in the control register.
Writing a “1” to LOS or NLOOP over the serial in-
terface has three effects:
1) The current interrupt on the serial interface
will be cleared. (Note that simply reading the
register bits will not clear the interrupt).
2) Output data bits 5, 6 and 7 will be reset as ap-
propriate.
3) Interrupts for the corresponding LOS and
NLOOP will be prevented from occurring.
Writing a “0” to either LOS or NLOOP enables the
corresponding interrupt for LOS and NLOOP.
Bits
765
Status Mode
0 0 0 Reset has occurred, or no program input
0 0 1 RLOOP active
0 1 0 LLOOP active
0 1 1 LOS has changed state since last Clear
LOS occurred
1 0 0 TAOS active
1 0 1 NLOOP has changed state since last
Clear NLOOP occurred
1 1 0 TAOS and LLOOP active
1 1 1 LOS and NLOOP have both changed
state since last Clear NLOOP and Clear
LOS
Table 3. Control Register 1 (0x10) Decoding
2.13 Power On Reset / Reset
Upon power-up, the IC is held in a static state until
the supply crosses a threshold of approximately
3 Volts. When this threshold is crossed, the device
will delay for about 10 ms to allow the power sup-
ply to reach operating voltage. After this delay, cal-
ibration of the transmit and receive sections
commences. Because power up conditions can vary
considerably, it is recommended that the device be
reset after the power supply has stabilized to ensure
a known initial operational condition.
The internal frequency generators can be calibrated
only if a reference clock is present. The reference
clock for the transmitter is provided by TCLK. The
reference for the receiver is either the crystal oscil-
lator or MCLK. If both the oscillator and MCLK
are active, MCLK will be used as the reference
source. The initial calibration should take less than
20 ms after pulses are input to the receiver.
In operation, the device is continuously calibrated,
making the performance of the device independent
of power supply or temperature variations. The
continuous calibration function forgoes any re-
quirement to reset the line interface when in opera-
tion. However, a reset function is available which
will reinitiate calibration and clear all registers and
clear the Network Loopback function.
In Host Mode, a reset is initiated by simultaneously
writing RLOOP and LLOOP to the register. The re-
set will set all registers to “0” and initiate a calibra-
tion. A reset will also set LOS high in the Short
Haul configuration.
In Hardware Mode, the CS61318 is reset by simul-
taneously setting RLOOP and LLOOP high for at
least 200 ns. Hardware reset will clear Network
Loopback functionality
2.14 Power Supply
The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies pro-
vide internal isolation. These pins should be decou-
DS441PP2
15

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