74VHC161284MTD Ver la hoja de datos (PDF) - Fairchild Semiconductor
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74VHC161284MTD Datasheet PDF : 11 Pages
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AC Electrical Characteristics
TA 40qC to 85qC
Symbol
Parameter
VCC 4.5V 5.5V
Units
Min
Max
tPHL
A1–A8 to B1–B8
tPLH
A1–A8 to B1–B8
tPHL
B1–B8 to A1–A8
tPLH
B1–B8 to A1–A8
tPHL
A9–A13 to Y9–Y13
tPLH
A9–A13 to Y9–Y13
tPHL
C14–C17 to A14–A17
tPLH
C14–C17 to A14–A17
tSKEW
LH-LH or HL-HL
tPHL
PLHIN to PLH
tPLH
PLHIN to PLH
tPHL
HLHIN to HLH
tPLH
HLHIN to HLH
tPHZ
Output Disable Time
tPLZ
DIR to A1–A8
tPZH
Output Enable Time
tPZL
DIR to A1–A8
tPHZ
Output Disable Time
tPLZ
DIR to B1–B8
tpEN
Output Enable Time
HD to B1–B8, Y9–Y13
tpDis
Output Disable Time
HD to B1–B8, Y9–Y13
tpEn–tpDis Output Enable-Output Disable
tSLEW
Output Slew Rate
tPLH
B1–B8, Y9–Y13
tPHL
tr, tf
tRISE and tFALL
B1–B8, Y9–Y13 (Note 8)
Note 8: Open Drain
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
6.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
30.0
ns
2.0
18.0
ns
2.0
18.0
2.0
25.0
ns
2.0
25.0
2.0
25.0
ns
2.0
25.0
2.0
28.0
ns
2.0
28.0
ns
20.0
ns
0.05
0.40
V/ns
0.05
0.40
120
ns
120
Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type.
(i) A1–A8 to B1–B8, A9–Y13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 10: This parameter is guaranteed but not tested, characterized only.
Figure
Number
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 9)
Figure 1
Figure 2
Figure 3
Figure 3
Figure 7
Figure 8
Figure 9
Figure 2
Figure 2
Figure 5
Figure 4
Figure 6
(Note 10)
Capacitance (Note 11)
Symbol
Parameter
CIN
Input Capacitance
CI/O
I/O Pin Capacitance
Note 11: Capacitance is measured at frequency
1 MHz.
Typ
Units
Conditions
5
pF
VCC 0.0V (HD, DIR, A9—A13, C14—C17, PLHIN and HLHIN)
12
pF
VCC 3.3V
5
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