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74FR543

Octal Latched Transceiver with 3-STATE Outputs

Fairchild Semiconductor 

Pin Descriptions

Pin Names

OEAB, OEBA

LEAB, LEBA

CEAB, CEBA

A0–A7

B0–B7

Description

Output Enable Inputs

Latch Enable Inputs

Chip Enable Inputs

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

Functional Description

The 74FR543 contains two sets of D-type latches, with

separate input and output controls for each. For data flow

from A-to-B, for example, the A-to-B Enable (CEAB) input

must be LOW in order to enter data from the A Port or take

data from the B Port as indicated in the Data I/O Control

Table. With CEAB LOW, a LOW signal on (LEAB) input

makes the A-to-B latches transparent; a subsequent LOW-

to-HIGH transition of the LEAB line puts the A latches in

the storage mode and their outputs no longer change with

the A inputs. With CEAB and OEAB both LOW, the B out-

put buffers are active and reflect the data present on the

output of the A latches. Control of data flow from B-to-A is

similar, but using the CEBA, LEBA and OEBA.

Data I/O Control Table

Inputs

Latch

CEAB LEAB OEAB Status

H

X

X

Latched

X

H

X

Latched

L

L

X Transparent

X

X

H

—

L

X

L

—

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Output

Buffers

High Z

—

—

High Z

Driving

Logic Diagram

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