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AD8310

Fast, Voltage-Out DC–440 MHz, 95 dB Logarithmic Amplifier

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AD8310

PRODUCT OVERVIEW

The AD8310 has six main amplifier/limiter stages. These six

cells and their and associated gm styled full-wave detectors

handle the lower two-thirds of the dynamic range. Three top-

end detectors, placed at 14.3 dB taps on a passive attenuator,

handle the upper third of the 95 dB range. The first amplifier

stage provides a low noise spectral density (1.28 nV/√Hz).

Biasing for these cells is provided by two references: one

determines their gain, and the other is a band gap circuit that

determines the logarithmic slope and stabilizes it against supply

and temperature variations. The AD8310 can be enabled or

disabled by a CMOS-compatible level at ENBL (Pin 7).

The differential current-mode outputs of the nine detectors are

summed and then converted to single-sided form, nominally

scaled 2 μA/dB. The output voltage is developed by applying

this current to a 3 kΩ load resistor followed by a high speed

gain-of-four buffer amplifier, resulting in a logarithmic slope of

24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered

voltage can be accessed at BFIN (Pin 6), allowing certain

functional modifications such as the addition of an external

postdemodulation filter capacitor and the alteration or

adjustment of slope and intercept.

SUPPLY

+INPUT

–INPUT

COMMON

VPOS

8mA

BAND GAP REFERENCE

AND BIASING

AD8310

ENBL

INHI

1.0kΩ

INLO

3

SIX 14.3dB 900MHz

AMPLIFIER STAGES

NINE DETECTOR CELLS

SPACED 14.3dB

COMM

INPUT-OFFSET

COMPENSATION LOOP

BFIN

MIRROR

2μA

/dB

2

3kΩ

+

–

3kΩ

VOUT

COMM 1kΩ

COMM

OFLT

33pF

COMM

ENABLE

BUFFER

INPUT

OUTPUT

OFFSET

FILTER

Figure 22. Main Features of the AD8310

The last gain stage also includes an offset-sensing cell. This

generates a bipolarity output current, if the main signal path

exhibits an imbalance due to accumulated dc offsets. This

current is integrated by an on-chip capacitor that can be

increased in value by an off-chip component at OFLT (Pin 3).

The resulting voltage is used to null the offset at the output of

the first stage. Because it does not involve the signal input

connections, whose ac-coupling capacitors otherwise introduce

a second pole into the feedback path, the stability of the offset

correction loop is assured.

The AD8310 is built on an advanced, dielectrically isolated,

complementary bipolar process. In the following interface

diagrams shown in Figure 23 to Figure 26, resistors labeled as

R are thin-film resistors that have a low temperature coefficient

of resistance (TCR) and high linearity under large-signal

conditions. Their absolute tolerance is typically within ±20%.

Similarly, capacitors labeled as C have a typical tolerance of

±15% and essentially zero temperature or voltage sensitivity.

Most interfaces have additional small junction capacitances

associated with them, due to active devices or ESD protection,

which might not be accurate or stable. Component numbering

in these interface diagrams is local.

ENABLE INTERFACE

The chip-enable interface is shown in Figure 23. The currents in

the diode-connected transistors control the turn-on and turn-

off states of the band gap reference and the bias generator. They

are a maximum of 100 μA when ENBL is taken to 5 V under

worst-case conditions. For voltages below 1 V, the AD8310 is

disabled and consumes a sleep current of less than 1 μA. When

tied to the supply or a voltage above 2 V, it is fully enabled. The

internal bias circuitry is very fast (typically <100 ns for either

off or on). In practice, however, the latency period before the

log amp exhibits its full dynamic range is more likely to be

limited by factors relating to the use of ac-coupling at the input

or the settling of the offset-control loop (see the following

sections).

40kΩ

ENBL 7

AD8310

TO BIAS

STAGES

2

COMM

Figure 23. Enable Interface

INPUT INTERFACE

Figure 24 shows the essentials of the input interface. CP and CM

are parasitic capacitances, and CD is the differential input

capacitance, largely due to Q1 and Q2. In most applications,

both input pins are ac-coupled. The S switches close when

enable is asserted. When disabled, bias current IE is shut off and

the inputs float; therefore, the coupling capacitors remain

charged. If the log amp is disabled for long periods, small

leakage currents discharge these capacitors. Then, if they are

poorly matched, charging currents at power-up can generate a

transient input voltage that can block the lower reaches of the

dynamic range until it becomes much less than the signal.

A single-sided signal can be applied via a blocking capacitor to

either Pin 1 or Pin 8, with the other pin ac-coupled to ground.

Under these conditions, the largest input signal that can be

handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V

supply; a 5 dBV input (2.5 V amplitude) can be handled with a

5 V supply. When using a fully balanced drive, this maximum

input level is permissible for supply voltages as low as 2.7 V.

Above 10 MHz, this is easily achieved using an LC matching

network. Such a network, having an inductor at the input,

usefully eliminates the input transient noted above.

Rev. E | Page 11 of 24

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