IDT72264 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72264
Integrated Device Technology
IDT72264 Datasheet PDF : 31 Pages
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IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
LD LOW and deactivate SEN or to set SEN LOW and deacti-
vate LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. From the time serial
programming has begun, neither partial flag will be valid until
the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves
either of the above criteria; PAF will be valid after two more
rising WCLK edges plus tPAF, PAE will be valid after the next
two rising RCLK edges plus tPAE (Add one more RCLK cycle
if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset regis-
ters can be read on the output lines when LD is set LOW and
72264 with MAC = GND (8,192 x 18–BIT)
17
12
0
72274 with MAC = GND (16,384 x 18–BIT)
17
13
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
17
12
0 17
13
0
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3218 drw 05a
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3218 drw 06a
72264 with MAC = Vcc (16,384 x 9–BIT)
72274 with MAC = Vcc (32,768 x 9–BIT)
8
7
08
7
0
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
5
08
6
0
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (MSB) REG.
00H
00H
8
7
08
7
0
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
5
08
6
FULL OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
00H
00H
NOTE:
3218 drw 05b
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
0
3218 drw 06b
11
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