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AD9260
(Rev.:2000)

High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate

Analog Devices 

AD9260–SPECIFICATIONS

DIGITAL SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)

Parameter

CLOCK1 AND LOGIC INPUTS

High-Level Input Voltage

(DVDD = +5 V)

(DVDD = +3 V)

Low-Level Input Voltage

(DVDD = +5 V)

(DVDD = +3 V)

High-Level Input Current (VIN = DVDD)

Low-Level Input Current (VIN = 0 V)

Input Capacitance

AD9260

+3.5

+2.1

+1.0

+0.9

± 10

± 10

5

LOGIC OUTPUTS (with DRVDD = 5 V)

High-Level Output Voltage (IOH = 50 µA)

+4.5

High-Level Output Voltage (IOH = 0.5 mA)

+2.4

Low-Level Output Voltage2 (IOL = 0.3 mA)

+0.4

Low-Level Output Voltage (IOL = 50 µA)

+0.1

Output Capacitance

5

LOGIC OUTPUTS (with DRVDD = 3 V)

High-Level Output Voltage (IOH = 50 µA)

+2.4

Low-Level Output Voltage (IOL = 50 µA)

+0.7

NOTES

1Since CLK is referenced to AVDD, +5 V logic input levels only apply.

2The AD9260 is not guaranteed to meet VOL = 0.4 V max for standard TTL load of IOL = 1.6 mA.

Specifications subject to change without notice.

ANALOG INPUT

INPUT CLOCK

S1

S2

tC

tCL

tCH

tDI

DATA OUTPUT

tH

DAV

tDS

tDAV

tOE

tOD

READ

CS

INPUT CLOCK

RESET

DAV

Figure 4a. Timing Diagram

tRES-DAV

tCLK-DAV

Figure 4b. RESET Timing Diagram

Units

V min

V max

V min

V max

µA max

µA max

pF typ

V min

V min

V max

V max

pF typ

V min

V max

–8–

REV. B

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