LTC1060
LTC1060 OFFSETS
Output Offsets
The DC offset at the filter bandpass output is always equal
to VOS3. The DC offsets at the remaining two outputs
(Notch and LP) depend on the mode of operation and
external resistor ratios. Table 5 illustrates this.
It is important to know the value of the DC output offsets,
especially when the filter handles input signals with large
Table 5
MODE
1,4
1a
1b
1c
VOSN
PIN 3 (18)
VOS1 [(1/Q) + 1 + ||HOLP||] – VOS3/Q
VOS1 [1 + (1/Q)] – VOS3/Q
VOS1 [(1/Q) + 1 + R2/R1] – VOS3/Q
VOS1 [(1/Q) + 1 + R2/R1] – VOS3/Q
2, 5
[VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)]
• [R4/(R2 + R4)] + VOS2[R2/(R2 + R4)]
2a
[VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)]
•
R4(1 + k)
R2 + R4(1 + k)
+
VOS2
R2
+
R2
R4(1
+
k)
;k
=
R6
R5 + R6
2b
[VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)]
•
R4k
R2 + R4k
+ VOS2
R2
R2 + R4k
;k
=
R6
R5 + R6
3, 4a
VOS2
dynamic range. As a rule of thumb, the output DC offsets
increase when:
1. The Q’s decrease.
2. The ratio (fCLK/f0) increases beyond 100:1. This is
done by decreasing either the (R2/R4) or the
R6/(R5 + R6) resistor ratios.
VOSBP
PIN 2 (19)
VOS3
VOS3
VOS3
VOS3
VOS3
VOSLP
PIN 1 (20)
VOSN – VOS2
VOSN – VOS2
~ (VOSN – VOS2) (1 + R5/R6)
~
(VOSN
–
VOS2)
(R5 + R6)
(R5 + 2R6)
VOSN – VOS2
VOS3
~ (VOSN
–
VOS2)
(R5 + R6)
(R5 + 2R6)
VOS3
~ (VOSN – VOS2) (1 + R5/R6)
VOS3
VOS1
1
+
R4
R1
+
R4
R2
+
R4
R3
– VOS2
R4
R2
– VOS3
R4
R3
PACKAGE DESCRIPTIO
N Package
20-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
( ) 8.255
+0.889
–0.381
.255 ± .015*
(6.477 ± 0.381)
1.040*
(26.416)
MAX
20 19 18 17 16 15 14 13 12 11
.125 – .145
(3.175 – 3.683)
.020
(0.508)
MIN
12 34 5678
NOTE:
INCHES
1. DIMENSIONS ARE MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
9 10
.120
(3.048)
MIN
.045 – .065
(1.143 – 1.651)
.005
(0.127)
MIN
.100
(2.54)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
.065
(1.651)
TYP
.018 ± .003
(0.457 ± 0.076)
N20 1002
1060fb
19