FX613P Ver la hoja de datos (PDF) - CML Microsystems Plc
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FX613P Datasheet PDF : 8 Pages
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Pin Number
FX613DW FX613P
Function
1
1
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 3.579545MHz Xtal or
externally derived telephone system clock (fXTAL) should be connected here.
Note - The operation of the FX613 without a suitable Xtal/Clock input may cause
device damage.
2
2
Xtal: The output of the on-chip clock oscillator inverter. See Figure 2.
3
3
No internal connection.
4
4
VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS.
5
5
Level In: The input for level discrimination. This input is internally biased to V ,
BIAS
signals must be a.c. coupled. The audio signal must be fed to both this pin and the
Signal In pin. Correct level detection determines the operation of this device (see
Principles of Decoder Operation), however to disregard the amplitude of the input
levels the FX613 may be permanently enabled by pulling this pin to VDD and disabled
by pulling to VSS.
6
6
Signal In: The input for frequency discrimination and decoding. This input is internally
biased to VBIAS, signals must be a.c. coupled. The audio signal must be fed to both this
pin and the Level In pin.
7
No internal connection.
8
7
VSS: Negative supply rail. Signal ground.
9
8
No internal connection.
10
No internal connection.
11
9
IRQ: This Interrupt Request output from the FX613 is ‘wire-OR able’ allowing the
interrupt outputs of other peripherals to be combined and connected to the Interrupt
input of a µProcessor. This input has a low-impedance pulldown to V when active and
SS
a high-impedance when inactive. An interrupt is produced on completion of a HI or LO
frequency measurement.
12
10
Serial Clock: The serial clock from the µProcessor. Data Out is clocked into the
µProcessor on the rising edge of the Serial Clock. See Data-Read Timing diagram.
13
11
Chip Select: A logic “0” at this input will select this device.
14
12
Data Out: The serial data output. Under the control of the Chip Select and Serial
Clock inputs, data should be read from this output in 6-bit blocks MSB (Bit-5) first.
If 8 serial clock pulses are applied, two additional logic “0s” will be output after Bit-0.
15
13
No internal connection.
16
14
VDD: Positive supply rail. A single, stable supply is required. Levels and voltages within
the FX613 are dependent upon this supply. This pin should be decoupled to V by a
SS
capacitor located close to the FX613 pins.
2
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