PBL 386 61/2
A
Preliminary
DC characteristics
B
C
B
C
D
D
VTR [V]
A:
IL (@ VTR = 0) = ILConst
ILConst (typ) = ILProg =
500
R (14)
LC
B, C: IL = ILConst VTR = VBatVirt - RFeed • (ILProg - 5•10-3)
D:
RFeed =
RSG
400
+ 40
E: IL ≈ 5 mA
F:
Apparent battery VApp (@IL = 0) = VBatVirt + 5•10-3 • RFeed
G: RFeedG = 2 • 25 Ω
H:
VTRMax = |VBat| - VBOH
J:
Virtual battery VBatVirt (@ IL = 5 mA) = |VBat| - 6.8(17)
Figure 13. Battery feed characteristics (without the protection resistors on the line).
E
J
G
F
HF
Power-up Sequence
No special power-up sequence is neces-
sary except that ground has to be present
before all other power supply voltages.
The digital inputs C1 and C2 are internal
pull-up terminals.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is inject-
ed into the RSN pin. Ground plane sur-
rounding the RSN pin is advisable.
Analog ground (AGND) should be con-
nected to battery ground (BGND) on the
PCB in one point.
RLC and RREF should be connected to
AGND with short leads. Pin LP, pin PSG
and pin AOV are sensitive to leakage cur-
rents. Pin AOV should be surrounded by a
guardring connected to AGND.
RSG and CLP connections to VBAT should
be short and very close to each other.
CB and CB2 must be connected with short
wide leads.
16