¡ Semiconductor
MSM7507-01/02/03
,TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
tXS
1
2
3
tSX
4
5
6
7
8
9
10
11
XSYNC
tWS
tXD1
tSD
tXD2
tXD3
PCMOUT
MSD D2
D3
D4
D5
D6
D7
D8
,When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.
Receive Timing
BCLK
tRS
RSYNC
1
2
3
4
5
6
7
tSR
tWS
8
9
tDS
tDH
PCMIN
MSD D2
D3
D4
D5
D6
D7
D8
10
11
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