CD4016BMS Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

fabricante

CD4016BMS

CMOS Quad Bilateral Switch

Intersil 

CD4016BMS

+10V

0

Vis

tr = tf = 20ns

ALL UNUSED TERMINALS

ARE CONNECTED TO VSS

VDD

CD4016BMS

200KΩ

VSS

Vos

CL

FIGURE 20. PROPAGATION DELAY TIME SIGNAL INPUT (VIS)

TO SIGNAL OUTPUT (VOS)

REP

RATE

VC

tr = tf = 20ns

VDD

VC

VDD

0

tr = tf = 20ns

CD4016BMS

Vos

Vis = VDD

ALL UNUSED TERMINALS

CL RL = 10KΩ

ARE CONNECTED TO VSS

VSS

FIGURE 21. MAXIMUM CONTROL-INPUT REPETITION RATE

VC

(13)

±

(1)

CD4016BMS

Vis = VDD

VSS

Vos

I I = 10µA

MEASURED ON BOONTON CAPACITANCE

BRIDGE MODEL 75A (1MHz)

VC = -5V

VSS = -5V

VDD = +5V

Vis

Cis

CIOS

Vos

Cos

SWITCH THRESHOLD VOLTAGE IS DEFINED AS THE VOLTAGE

APPLIED TO A TRANSMISSION GATE CONTROL WHICH CAUSES

10µA OF TRANSMISSION GATE CURRENT

FIGURE 22. SWITCH THRESHOLD VOLTAGE

ALL UNUSED TERMINALS

ARE CONNECTED TO VSS

FIGURE 23. CAPACITANCE CIOS AND COS

VDD

VC

0

tr = tf = 20ns

Vis = VDD OR VSS

VDD

CD4016BMS

ALL UNUSED TERMINALS

ARE CONNECTED TO VSS

VSS

Vos

CL RL

VSS

VDD

50%

VC

tPZH

Vos

10%

tPZL

Vos

10%

FIGURE 24. TURN-ON PROPAGATION DELAY CONTROL INPUT

RL TO VSS

Vis TO VDD

RL TO VDD

Vis TO VSS

Chip Dimensions and Pad Layout

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 i

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

-3

7-742

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